1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a metal-oxide semiconductor (MOS) transistor.
2. Description of Related Art
Fabrication of MOS transistors is an essential part in a very large scale integration (VLSI) fabrication. The MOS transistors are widely used in all various semiconductor devices, such as microprocessors, memory devices, power sources and so on. The MOS transistors are the key elements in the semiconductor devices. A typical fabrication method of MOS transistor includes first forming several isolation structures on a semiconductor substrate to form active areas. Each active area is the area between two isolation structures. A MOS transistor is to be formed on one active area. The isolation structures can prevent carriers from drifting between two neighboring MOS transistors. A formation of the MOS transistor further includes forming a gate structure and forming two interchangeable source/drain regions respectively at each side of the gate structure in the semiconductor substrate. Then, a dielectric layer is formed over the substrate, a contact is formed in the dielectric layer to have an electric coupling with desired one of the interchangeable source/drain regions. An interconnect structure is subsequently formed over the dielectric layer. The interconnect structure usually includes multilevel interconnects. The lowest level is electrically coupled to the MOS transistor through the contact. Each different interconnect level is electrically coupled to each other through a via structure.
The conventional method for fabricating the MOS transistor is complicate. As the device integration increases, it becomes difficult to fabricate the MOS transistor. This difficulty can be seen in the following example of a conventional MOS transistor. FIGS. 1A-1G are cross-sectional views of a portion of a substrate, schematically illustrating conventional fabrication processes for forming a MOS transistor.
In FIG. 1A and FIG. 1B, a pad oxide layer 102 is formed over a semiconductor substrate 100. A silicon nitride layer 104 is formed over the pad oxide layer 102. In FIG. 1B, a shallow trench 105 is formed in the substrate 100 by patterning the silicon nitride layer 104, the pad oxide layer 102, and the substrate 100. The patterning process includes photolithography and anisotropic etching. The anisotropic etching process etches the silicon nitride layer 104, the pad oxide layer 102 and the substrate 100, in which the silicon nitride layer 104 and the pad oxide layer 102 respectively become a silicon nitride layer 104a and a pad oxide layer 102a. An oxide layer 108 is formed over the substrate 100 so that the trench 105 is also filled.
In FIG. 1B and 1C, a chemical mechanical polishing (CMP) process is performed to polish the oxide layer 108 so as to expose the silicon nitride layer 104a. The silicon nitride layer 104a and the pad oxide layer 102a are respectively removed by wet etching with different etchant solution. The oxide layer 108 is also etched during wet etching, resulting in a remaining portion, that is, an oxide layer 108a to fill the trench 105. A shallow trench isolation (STI) structure is formed. The substrate 100 other than the trench 105 is exposed.
In FIG. 1D, a MOS transistor is to be subsequently formed. A thermal oxidation process is performed to form an oxide layer 110, serving as a gate oxide layer later, over the substrate 100. A polysilicon layer 112 is formed on the oxide layer 110 by chemical vapor deposition (CVD).
In FIG. 1D and FIG. 1E, the oxide layer 110 and the polysilicon layer 112 are patterned and respectively become a gate oxide layer 110a and a gate polysilicon layer 112a, both of which form together as a gate structure. A light ion implantation process is performed to two lightly doped regions respectively at each side of the gate structure in the substrate 100. A spacer 116 is formed on each sidewall of the gate structure. A heavy ion implantation process is performed to form a heavily doped region on the lightly doped region. Two interchangeable source/drain regions 118 with a lightly doped drain (LDD) structure are formed in the substrate 100 at each side of the gate structure, which includes the gate oxide layer 110a and the gate polysilicon layer 112a. In order to reduce sheet resistance on the interchangeable source/drain regions 118, a self-aligned silicide (Salicide) layer 115 is necessarily formed on the interchangeable source/drain regions 118, and a Salicide layer 114 is necessarily formed on the gate polysilicon layer 112a. A MOS transistor including the gate polysilicon layer 112a, the gate oxide layer 110a and the interchangeable source/drain regions 118 is formed. A dielectric layer 120 is formed over the substrate 100 so as to isolate the MOS transistor from a subsequent formation of an interconnect structure.
In FIG. 1E and FIG. 1F, the dielectric layer 120 is planarized and patterned to form a dielectric layer 120a. There are, for example, two contact openings 122 and 123 formed in the dielectric layer 120a so as to respectively expose the Salicide layer 115 and the Salicide layer 114. A metal layer 124 is deposited over the substrate 100 so that the contact openings 122, 123 are also filled.
In FIG. 1F and FIG. 1G, a portion of the metal layer 124 other than the contact openings 122, 123 is removed by chemical mechanical polishing (CMP). The dielectric layer 120a is exposed and a remaining portion of the metal layer 124 becomes a metal plug 124a filled in the contact opening 122, and a metal plug 124b filled in the contact opening 123.
In the conventional method described above, as the oxide layer 108a is formed as shown in FIG. 1C, a recess structure 150 usually occurs at the top corners 140, resulting from the wet etching. The oxide layer 108a has a weaker structure at the top corners 140 due to a discontinuation of material. When the wet etching process with its isotropic property is performed to remove the silicon nitride layer 104a and the pad oxide layer 102a to form the oxide layer 108a, and a subsequent cleaning process is routinely performed, the recess structure 150 occurs inevitably. The recess structure 150 may cause a kink effect, which further causes a sub-threshold voltage when a polysilicon gate is formed later.
Moreover, the Salicide layer 115 usually is formed by forming a metal layer over the substrate, and performing a thermal process to cause a reaction between the silicon material in the substrate 100 and the metal layer and form the Salicide layers 114, 115. Then the portion of the metal layer without reaction is removed. Even through the Salicide layer 115 can reduce sheet resistance, it consumes the junction depth of the interchangeable source/drain regions 118, resulting in a charge leakage.
Furthermore, as the device integration increases, the device dimension is reduced. When device critical dimension is down to a deep sub-micron level, it is very difficult to form the Salicide layer 114 on the gate polysilicon layer 112a. In addition, the intrinsic gate resistance of the gate polysilicon layer 112a is accordingly increased as the gate dimension is reduced, resulting in a longer response time of the MOS transistor.
Currently, in order to reduce the gate resistance, a metallic gate is developed to take the place of the gate polysilicon layer 112a but this alternative conventional method may easily cause an acid-tank contamination due to a necessary etching process to form the metallic gate.
Moreover, since the depth of the contact opening 123 is smaller than the depth of the contact opening 122, when the etching process is performed to simultaneously form the contact openings 122, 123, the formation of the contact opening 123 is earlier than the formation of the contact opening 122. In order to complete the formation of the contact opening 122 to expose the Salicide layer 115, the Salicide layer 114 exposed by the opening 123 may be over etched, resulting in an etching damage. The electrical property on the Salicide layer 114 is therefore degraded.
Moreover, as device integration increases, the aspect ratio (AR), which is a ratio of depth to bottom width, of the contact opening 122 increases also, and a borderless contact strategy is also applied. The borderless contact strategy allows the contact opening 122 to be partially located on the interchangeable source/drain regions 115 without precisely alignment. In order to form a contact plug in a high AR contact opening 122 with sufficient step coverage capability, the top corners of the high AR contact opening 122 need to be rounded, or the sidewall of the high AR contact opening needs to be slanted to form a taper contact with a taper angle of 87.degree.. Since the taper contact opening needs wider top width, the borderless contact strategy is applied. If the device dimension is maintained to be still high integration, both the rounded contact opening and the taper contact opening need a higher fabrication capability to achieve it.
On the other hand, if a misalignment in photolithography occurs on formation of the contact opening 122, the contact opening 122 may cover a portion of the STI structure 108a, resulting in an undesired etching on the STI structure 108a and causing a current leakage.